And, when coupled with functional testing, the fault coverage for the entire process is as good as or better than in-circuit testing alone. 加上功能测试,这个过程中检测到的故障率要比单独进行在线测试故障发现率大。
As an important white-box test method, the basic path test has higher fault coverage. 基本路径测试是一种重要的白盒测试技术,具有较高的故障覆盖率。
Improvement of testability: For the purpose of reducing test cost and obtaining higher fault coverage, several Design-for-Testability ( DFT) methodologies of the circuit are concerned. 可测性的改善。为了降低测试成本和提高故障覆盖率,必须对原芯核电路进行可测性设计,为此本文研究了几种用以提高电路可测性的措施。
The dynamic power supply current ( IDDT) is a new window through which we can observe the switching activities in digital circuits. IDDT testing methods make possible further increasing the fault coverage. 动态电流提供了一个观测电路内部开关性能的新的窗口,动态电流测试方法为进一步提高故障覆盖率提供了可能。
Conventional STUMPS spends much time for testing, and its fault coverage is not high enough. 传统的STUMPS测试方法,存在测试时间长和故障覆盖率不够高的缺点。
For actual circuits the fault coverage obtained from this approach agrees favorably with the fault simulation results. 对一些实际的电路,利用此法所获得的故障覆盖与故障模拟结果非常吻合。
The experimental results show that comparing with existing methods, the method in this paper can improve the fault coverage of the resulting test suite and is feasible and effective. 实验结果表明:与原有方法相比,该方法可以有效地提高测试集的错误覆盖,并具备一定的可行性和有效性。
The generation strategy combines the merits of both data flow test and control flow test, having both higher fault coverage of tests and complete test for the data part of the communication protocol so as to advance the efficiency of conformance test. 该生成策略同时结合了数据流测试和控制流测试的优点,既具有比较高的错误覆盖率,又对通信协议中的数据部分进行了充分的测试,从而提高了一致性测试的效率。
A new, simple and effective DFT technology for the memory units in ASIC is presented in this paper to test some untestable faults and improve the fault coverage ratio. 本文提出了一种简洁有效的、针对ASIC中记忆部件的易测试性设计技术,可消除部分不可测故障,提高故障覆盖率。
It can increase the fault coverage, reduce testing cost and improve the quality and reliability of ICs. 它通过从电源电流信号中提取有效的信息来进行故障诊断,能够提高故障覆盖率,降低测试成本并提高集成电路产品的质量与可靠性。
This test method has very high fault coverage and is suitable for latch BIST implementation. 在可测性设计方面,提出了一种新的测试大块锁存器的测试方法,有很高的故障覆盖率,且适合做内建自测试;
To enhance the reliability and the fault coverage of the test results, a local error diagnostic mechanism was introduced into dynamic protocol conformance test, a new dynamic test method was proposed, whose principle and correctness was analyzed on determinate finite state machine model. 为提高测试结果的可靠性和错误覆盖率,在动态协议一致性测试过程中引入局部错误诊断机制,提出了一种新的动态测试方法,并在确定有限状态机模型下分析其原理及正确性。
Diagnostic algorithms and diagnostic tactic should steer a middle course among diagnostic time, fault coverage and area expense. 诊断算法和诊断策略要在诊断时间、故障覆盖率、面积开支之间进行权衡。
The first model supposes every test case has equal fault detective ability and can get the same fault coverage. 第一个模型假设每个测试用例有相同的故障检测能力,能获得相同的故障覆盖率;
This paper aims at achieving higher fault coverage for circuits under test with less hardware overhead and time consumption. 为了用较少的硬件和测试时间开销获得对被测电路较高的故障覆盖,提出了一种数字集成电路测试中多扫描链的配置方法。
In this paper a new test pattern generation method is proposed, which can greatly reduce the power dissipation during test mode and has no impact on the fault coverage. 本文提出了一种面向功耗优化的伪随机测试向量生成方法,在保证故障覆盖率的条件下,大大降低了测试功耗。
It has been proved that this design can meet the two targets of the IP core-based SOC test, low test costs and high fault coverage. 经验证,用BS-TW结构实现的DFT能同时实现IP复用SOC的低测试开销和高故障覆盖率的目标。
As an enhancement of these methods, current testing can increase the fault coverage and make higher the reliability of ICs. 作为这些方法的一个补充,电流测试方法能够提高故障的覆盖率,提高产品的可靠性。
The proposed method can generate simplified test patterns with high fault coverage, and can detect multiple faults as many as possible. 新方法可生成精简的、故障覆盖率高的测试图形,并尽可能多地检测多重故障。
The fault detection method we designed not only decreases time of detection but also increases the veracity of fault location to increase the ratio of fault coverage. 所提出的检测方法不仅减少检测时间,还提高了故障定位的准确度和故障覆盖率。
The march 13n test algorithm insures 100% fault coverage for stuck-at faults, transition faults, address decoder faults and stuck-open faults. 所采用的march13n算法确保了对固定型故障、跳变故障、地址译码故障和读写电路的开路故障均达到100%的故障覆盖率。
The final target of the project is what achieve high fault coverage and efficiently test for mass produce. 本项目研发的最终目标是实现高效率、高故障覆盖率的线上批量测试技术。
How to save test time and guarantee high fault coverage during high-speed test are big problems. 该存储器所具有的优势给测试带来了挑战,如何节省测试时间和芯片管脚,在高速测试中保证高故障覆盖率成为重要的问题。
The test results certify that the new method has high fault coverage and can diagnose some faults which traditional methods with logic testing can not detect. 实验结果证明了新的融合测试方法具有故障覆盖率高的特点,能诊断传统逻辑测试法难以检测到的部分故障。
It demonstrated that the method can drastically reduce test application time while maintaining low test power and high fault coverage. 实验结果表明:在较低的测试功耗和保持故障覆盖率不变的前提下提出方法大幅度地降低了测试应用时间和测试数据量,从而降低了测试费用。
With ensuring the observable and controllable coverage of the system, DFT could improve the fault coverage and reduce test time. 可测试性设计方法在保证系统的可观测性和可控制性的前提下,能够提高测试覆盖率,缩短测试时间。
Each function of the chip was verified as well as fault coverage of the chip was analyzed. 对该芯片的各个功能进行了验证以及对芯片进行了故障覆盖率分析。
However the memory vendor recommended the March-lr algorithm to get high fault coverage. 但K68的存储器提供商建议使用March-lr算法来达到较高的故障覆盖率。
The paper also makes fault coverage for the design. Finally, the paper looks forward to the SoC test technology. 同时也进行了故障覆盖率的仿真。最后本文对SoC测试技术的未来发展方向进行了展望。
In conclusion, the design method of testability for mixed-signal chip with lower cost, higher fault coverage and higher reliability is the demand of further development of system level chip. 总之,具有低廉的测试成本、尽可能高的故障覆盖率和高度可靠的混合信号芯片的可测性设计方法将是系统级芯片进一步发展的要求。